As the operating voltages for CMOS transistor circuits have decreased, variations in the threshold voltages for the transistors have become more significant. Although low operating voltages offer the potential for reduced power consumption, threshold voltage variations due to process and environmental variables often prevent optimum efficiency and performance from being achieved due to increased leakage currents.
Threshold voltage variations may be compensated for by body biasing. In typical CMOS transistors, the body of the transistor is connected to a supply rail (e.g., Vss for NMOS, and Vdd for PMOS). In this configuration the transistor is often treated as a three terminal device.
In static CMOS gates usually consist of “nstacks” and “pstacks”, series/parallel combinations of transistors of the same type rooted at Vss for NMOS and Vdd for PMOS. Only the transistors at the root of the stack have their bodies tied to their sources.
Body biasing introduces a bias potential between the bulk and the source of the transistor that allows the threshold voltage of the transistor to be adjusted electrically. The purpose of body biasing is to compensate for 1) process variations; 2) temperature variations; 3) supply voltage variations; 4) changes in frequency of operation; and 5) changing levels of switching activity.
Whereas the typical CMOS transistor is a three-terminal device, the body biased CMOS transistor is a four-terminal device, and thus requires a more complex interconnect scheme. Connections for body biasing may be made on the substrate surface using conventional metal/dielectric interconnects similar to those used for typical gate, drain, and source connections, or they may be made using buried complementary well structures.
For example, in a p-type substrate with a population of surface n-wells that contain p-channel field effect transistors (PFETs), a buried n-type layer may be formed in the substrate at a depth that allows for contact with the bottom of the n-wells, while providing sufficient clearance with respect to n-channel field effect transistors (NFETs) in the substrate.
Prior Art FIG. 1 shows a conventional CMOS substrate with a buried n-well. A p-type substrate 105 supports an NFET 110 and a PFET 120. The NFET 110 comprises a gate 112, source 113, and drain 114. The PFET 120 resides in an n-well 115, and comprises a gate 122, drain 123, and a source 124. Body bias is provided to the PFET 122 by a buried n-well 125 that is located a distance D below the surface of the substrate. Distance D is typically one micron or less.
A contact 135 comprising an implanted via and contact metal is typically used to establish external contact to the buried n-well. A plurality of contacts may be used to reduce the resistance in the bias path.
A body bias contact 140 is provided on the bottom of the substrate 105 for body biasing NFET 110. An aperture 130 is provided in the buried n-well 125 so that the bias potential reaches the NFET 110. It is preferable that a body biased NFET be located near an aperture 130 so that the bias path resistance is optimized.
In a retrofit application of deep n-well (DNW), if an n-well can not be reached, the nonoptimality of the leakage contributed by a few isolated PFETs will be negligible. The only constraint is that the unreachable circuits must be robust enough to operate correctly without bias when the transistor thresholds are reduced to increase performance.
Although the prior art discusses the possibility of using many buried layers in a substrate for interconnection purposes, the prior art has failed to appreciate the limitations of using deep patterned layers for interconnection to surface devices.